AAS supports various verification environment types:

Co-Simulation
- SV-PY:  SystemVerilog-Python co-sim. reference model implemented in Python
- SV-C: SystemVerilog-C co-sim. Tests are written in C, DUT contains CPU.

Verification Strategy
- Random Coverage Driven – major metric for sign-off based on coverage, functional and code coverage. Tests are random and directed ones.
- Tests Driven – Feature list and test scenarios which covers all features. 

Verification Capabilities