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Build Your Career at Avnet ASIC

Build Your Career at Avnet ASIC

At Avnet ASIC, we’re a dynamic, family like team where everyone’s voice matters. You’ll find a supportive culture, real mentorship, and the kind of collaboration that helps you grow — personally and professionally.

Work on the edge of innovation Design and deliver ASICs for attractive industry segments: perceptual computing, AI, communications, and more. Tackle complex, real world challenges and see your impact on products that move the world forward.
Shape ASIC future From concept to production, your work here helps set the pace for the local ecosystem. If you’re driven to make a tangible mark on Israel’s semiconductor industry, this is the place to do it.
Your next career chapter Join our team — it’s about people, and about creating technology that matters.

Open Positions

Explore the roles below. Expand a card to see requirements and “advantage” skills.

Experienced RTL Design Team LeaderRTL • Architecture • Leadership

Requirements

  • BSc. in Electrical Engineering (from known university)
  • Minimum 8 years of experience – Must!
  • Logic design project leader or chip architect
  • Hands on RTL design with Verilog or System Verilog
  • Micro architecture definition in CPU/DSP environment
  • Knowledge in verification (System Verilog, System-C etc.)

Advantage

  • RTL for FPGA and emulation
  • AC spec definition
  • SDC timing constraints write from spec
  • RT C, C++, assembly
  • SoC design experience: DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, ARC
  • Hands on: Spyglass, synthesis, STA, DFT
  • Technical customer support or interface experience
Experienced RTL DesignerSystemVerilog • UVM • Low Power

Requirements

  • 5 years hands-on System Verilog RTL coding
  • Experience with tools such as VCS, Verdi, and Spyglass
  • Experience debugging and working with validation using UVM
  • Experience with Multiple Clock Domains, multiple power domains, low power design

Advantage

  • SoC design: DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, ARC CPU
  • Clock crossing interfaces like Gray FIFO, CDC
  • Pre-silicon validation, UVM coding, validation tools and methodology
  • Full design cycle: BE design, synthesis, STA, floorplanning, DFT integration
  • RTL for FPGA and emulation
  • Software experience and C/C++ for reference model development; drivers for ARM SoC IPs
Experienced Verification EngineerSoC Verification • SystemVerilog • UVM

Requirements

  • 5 years of SoC System Verilog validation experience
  • Hands on experience using UVM to verify ASICs
  • Advanced knowledge of System Verilog test-bench language
  • Experience with verification methodologies/tools: simulators, waveform viewers, build/run automation, coverage collection, gate level simulations, formal validation

Advantage

  • Full digital design verification cycle — from spec through bring-up/prototyping and debug
  • Performance/power validation, digital design (RTL), and formal verification
  • SoC design: DDR, USB, MIPI, ARM subsystem, AMBA, AXI, AHB, DSP, ARC CPU
  • Mixed-signal verification for IPs such as PHYs, A2D, PLLs, etc.
  • Software and C/C++ for reference model development; drivers for ARM SoC IPs
Experienced Backend Project LeaderP&R • Timing Closure • Technical Leadership

Requirements

  • BSc. in Electrical Engineering (from known university)
  • Minimum 5 years of experience – Must!
  • Technical management experience – Advantage

Advantage

  • Floorplan and Place & Route, block & top level
  • Timing closure & debug, STA, SDC insertion and analysis
  • Clock Tree Synthesis
  • Power Grid Analysis
  • LVS/DRC debug
  • DFT & ATPG methodologies (BIST, Scan, JTAG)
  • CAD: Synopsys preferred, Cadence acceptable
Experienced Backend EngineerP&R • STA • Power / DRC

Requirements

  • BSc. in Electrical Engineering (from known university)
  • Minimum 2 years of experience – Must!

Advantage

  • Floorplan and Place & Route
  • Timing closure & debug, STA
  • Clock Tree Synthesis
  • Power Grid Analysis
  • LVS/DRC debug
  • Experience with DFT – Advantage
  • Experience with ICC – Advantage
Experienced DFT EngineerScan • ATPG • MBIST • JTAG

Requirements

  • BSc. in Electrical Engineering (from known university)
  • Minimum 3 years of experience on DFT – Must!

Advantage

  • DFT methodologies: Scan, ATPG, @speed, memory BIST, I/O DFT
  • Scan insertion and ATPG for stuck-at, transition delay, bridging, IDDQ
  • Coverage improvement & DFT DRC using FTMAX / DFTCompiler / TetraMAX / SpyglassDFT; MBIST using Tessent MBIST (MentorGraphics)
  • Strong knowledge of JTAG 1149.1, 1149.6 and P1500 standards
  • Hands on design & implementation of DFT features
  • In depth understanding of DFT tool flows (Synopsys / Mentor / equivalent); Tessent MBIST is an added advantage
  • End-to-end design flow experience (conception to TO to production) in DFT
  • Perl or other UNIX scripting for flow automation
  • Formal equivalence checking
  • Setting up and running gate-level simulations

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Assembly & Test

AAS's manufacturing service portfolio includes handling of the assembly and test. We provide a complete solution from package type choice, package design, test program development and transfer to production through delivery of the assembled & tested devices to the customers.

We provide our own test development services. Our key assembly and test vendors are ASE Taiwan, Amkor Korea, Salland Netherlands, Integra US.

A dedicated manufacturing manager monitors all assembly and test vendor activities and provides customers with comprehensive information on product advancement in line. Our manufacturing team monitors the yields of front and end line, as well as final test yield.

We work in collaboration with the vendor to optimize the test program and to keep yields stable and improving. We match final test yield with the wafer sort yield to ensure the best quality and reliability of the product and production lines.

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RMA

Our standard RMA procedure is depicted below:
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Fabrication

Fabrication services include forecast coordination, allocation, scheduling, capacity, and paperwork issues with the FAB. The appointed manufacturing manager monitors all activities in the FAB and provides customers with all the information on product advancement in line.

 Our manufacturing team will examine PCM data to ensure that the wafers are within the specification and use this data for correlation with the final test yield.

We are well equipped to handle a swift ramp-up to mass production, and we have the expertise to ensure timely delivery of your product.

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